The high performance of the PIC16F62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional Von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single-word instructions.

Program Memory Type Flash
Program Memory Size (Kbytes) 1.75
RAM 224
Data EEPROM (bytes) 128
I/O 16
Low voltage programming
low speed Clock mode
Programmable BOR
4MHz internal RC oscillator
on-chip voltage reference
128 bytes of EEPROM Data Memory

Not ROHS compliant.